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FPGA based Prototyping of Next Generation Forward Error Correction
FPGA based Prototyping Generation Forward Error Correction
2015/7/15
The concatenation of LDPC and RS codes has been demonstrated using a real-time FPGA prototype.A net coding gain of 9.0dB for 31.3-Gb/s was achieved with 20.5% redundancy for an input BER of 10 -2 .